​High Performance Silicon Nanotube Tunneling FET for Ultra-Low Power Logic Applications - Hossain M. Fahad and Muhammad M. Hussain

To increase typically low output drive currents from tunnel FETs, we show silicon’s vertical nanotube architecture based FET’s effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon nanotube tunneling FET shows sub-60 mV/dec sub-threshold slope and ultra-low off-state leakage current and a higher drive-current compared to gate-all-around (GAA NW) nanowire silicon tunnel FETs.